document number: 91236 www.vishay.com s-pending-rev. b, 23-jul-08 work-in-progress 1 power mosfet irfp460n, sihfp460n vishay siliconix features ? low gate charge q g results in simple drive requirement ? improved gate, avalanche and dynamic dv/dt ruggedness ? fully characterized capacitance and avalanche voltage and current ? effective c oss specified ? lead (pb)-free available applications ? switch mode power supply (smps) ? uninterruptible power supply ? high speed power switching typical smps topologies ? full bridge ? power factor correction boost notes a. repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. starting t j = 25 c, l = 1.8 mh, r g = 25 , i as = 20 a (see fig. 12). c. i sd 20 a, di/dt 140 a/s, v dd v ds , t j 150 c. d. 1.6 mm from case. product summary v ds (v) 500 r ds(on) ( )v gs = 10 v 0.24 q g (max.) (nc) 124 q gs (nc) 40 q gd (nc) 57 configuration single n -channel mosfet g d s to-247 g d s a v aila b le rohs * compliant ordering information package to-247 lead (pb)-free irfp460npbf SIHFP460N-E3 snpb irfp460n sihfp460n absolute maximum ratings t c = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds 500 v gate-source voltage v gs 30 continuous drain current v gs at 10 v t c = 25 c i d 20 a t c = 100 c 13 pulsed drain current a i dm 80 linear derating factor 2.2 w/c single pulse avalanche energy b e as 340 mj repetitive avalanche current a i ar 20 a repetitive avalanche energy a e ar 28 mj maximum power dissipation t c = 25 c p d 280 w peak diode recovery dv/dt c dv/dt 5.0 v/ns operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (p eak temperature) for 10 s 300 d mounting torque 6-32 or m3 screw 10 lbf in 1.1 n m * pb containing terminations are not rohs compliant, exemptions may apply
www.vishay.com document number: 91236 2 s-pending-rev. b, 23-jul-08 irfp460n, sihfp460n vishay siliconix notes a. repetitive rating; pulse width limited by maximum junction temper ature (see fig. 11). b. pulse width 300 s; duty cycle 2 %. c. c oss eff. is a fixed capacitance that gi ves the same charging time as c oss while v ds is rising from 0 to 80 % v ds . thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-ambient r thja -40 c/w case-to-sink, flat, greased surface r thcs 0.24 - maximum junction-to-case (drain) r thjc -0.45 specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 500 - - v v ds temperature coefficient v ds /t j reference to 25 c, i d = 1 ma - 580 - mv/c gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 3.0 - 5.0 v gate-source leakage i gss v gs = 30 v - - 100 na zero gate voltage drain current i dss v ds = 500 v, v gs = 0 v - - 25 a v ds = 400 v, v gs = 0 v, t j = 125 c - - 250 drain-source on-state resistance r ds(on) v gs = 10 v i d = 12 a b - - 0.24 forward transconductance g fs v ds = 50 v, i d = 12 a 10 - - s dynamic input capacitance c iss v gs = 0 v, v ds = 25 v, f = 1.0 mhz, see fig. 5 - 3540 - pf output capacitance c oss - 350 - reverse transfer capacitance c rss -30- output capacitance c oss v gs = 0 v v ds = 1.0 v, f = 1.0 mhz - 3930 - v ds = 400 v, f = 1.0 mhz - 95 - effective output capacitance c oss eff. v ds = 0 v to 400 v c - 200 - total gate charge q g v gs = 10 v i d = 20 a, v ds = 400 v see fig. 6 and 13 b - - 124 nc gate-source charge q gs --40 gate-drain charge q gd --57 turn-on delay time t d(on) v dd = 250 v, i d = 20 a r g = 4.3 , r d = 13 , see fig. 10 b -23- ns rise time t r -87- turn-off delay time t d(off) -34- fall time t f -33- drain-source body diode characteristics continuous source-drain diode current i s mosfet symbol showing the integral reverse p - n junction diode --20 a pulsed diode forward current a i sm --80 body diode voltage v sd t j = 25 c, i s = 20 a, v gs = 0 v b --1.8v body diode reverse recovery time t rr t j = 25 c, i f = 20 a, di/dt = 100 a/s b - 550 825 ns body diode reverse recovery charge q rr - 7.2 10.8 c forward turn-on time t on intrinsic turn-on time is neglig ible (turn-on is dominated by l s and l d ) s d g
document number: 91236 www.vishay.com s-pending-rev. b, 23-jul-08 3 irfp460n, sihfp460n vishay siliconix typical characteristics 25 c, unless otherwise noted fig. 1 - typical output characteristics fig. 2 - typical output characteristics fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature 0.001 0.01 0.1 1 10 100 0.1 1 10 100 20 s pulse w idth t = 25 c j top bottom v gs 15 v 12 v 10 v 9.0 v 8 .0 v 7.0 v 6.0 v 5.0 v v , drain-to-so u rce v oltage ( v ) i , drain-to-so u rce c u rrent (a) ds d 5.0 v 0.1 1 10 100 0.1 1 10 100 20 s pulse w idth t = 150 c j top bottom v gs 15 v 12 v 10 v 9.0 v 8 .0 v 7.0 v 6.0 v 5.0 v v , drain-to-so u rce v oltage ( v ) i , drain-to-so u rce c u rrent (a) ds d 5.0 v 0.1 1 10 100 5 6 7 8 9 10 11 v = 50 v 20 s pulse w idth ds v , gate-to-so u rce v oltage ( v ) i , drain-to-so u rce c u rrent (a) gs d t = 25 c j t = 150 c j -60 -40 -20 0 20 40 60 8 0 100 120 140 160 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 t , j u nction temperat u re ( c) r , drain-to-so u rce on resistance ( n ormalized) j ds(on) v = i = gs d 10 v 20a
www.vishay.com document number: 91236 4 s-pending-rev. b, 23-jul-08 irfp460n, sihfp460n vishay siliconix fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area 1 10 100 1000 v ds , drain-to-so u rce v oltage ( v ) 10 100 1000 10000 100000 c , c a p a c i t a n c e ( p f ) coss crss ciss v gs = 0 v , f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd 0 20 40 60 8 0 100 120 140 0 4 8 12 16 20 q , total gate charge (nc) v , gate-to-so u rce v oltage ( v ) g gs for test circuit see figure i = d 13 20a v = 100 v ds v = 250 v ds v = 400 v ds 0.1 1 10 100 0.2 0.4 0.6 0. 8 1.0 1.2 1.4 1.6 v ,so u rce-to-drain v oltage ( v ) i , re v erse drain c u rrent (a) sd sd v = 0 v gs t = 25 c j t = 150 c j 10 100 1000 10000 v ds , drain-toso u rce v oltage ( v ) 0.1 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) t a = 25c t j = 150c single p u lse 1msec 10msec operatio n i n this area limited by r ds (on) 100 sec
document number: 91236 www.vishay.com s-pending-rev. b, 23-jul-08 5 irfp460n, sihfp460n vishay siliconix fig. 9 - maximum drain current vs. case temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction-to-case fig. 12a - unclamped inductive test circuit fig. 12b - unclamped inductive waveforms 25 50 75 100 125 150 0 5 10 15 20 t , case temperat u re ( c) i , drain c u rrent (a) c d v ds p u lse w idth 1 s d u ty factor 0.1 % r d v gs r g d.u.t. 10 v + - v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f 0.001 0.01 0.1 1 0.00001 0.0001 0.001 0.01 0.1 1 n otes: 1. d u ty factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c p t t dm 1 2 t , rectang u lar p u lse d u ration (s) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50 si n gle pulse (thermal respo n se) a r g i as 0.01 t p d.u.t. l v ds + - v dd dri v er a 15 v 20 v t p v ds i as
www.vishay.com document number: 91236 6 s-pending-rev. b, 23-jul-08 irfp460n, sihfp460n vishay siliconix fig. 12c - maximum avalanche energy vs. drain current fig. 13a - basic gate charge waveform fig. 13b - gate charge test circuit 25 50 75 100 125 150 0 150 300 450 600 750 starting t , j u nction temperat u re ( c) e , single p u lse a v alanche energy (mj) j as i d top bottom 8 .9a 12.6a 20a q g q gs q gd v g charge 10 v d.u.t. v ds i d i g 3 ma v gs 0.3 f 50 k 0.2 f 12 v c u rrent reg u lator same type as d.u.t. c u rrent sampling resistors + -
document number: 91236 www.vishay.com s-pending-rev. b, 23-jul-08 7 irfp460n, sihfp460n vishay siliconix fig. 14 - for n-channel vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91236 p. w . period di/dt diode reco v ery d v /dt ripple 5 % body diode for w ard drop re-applied v oltage re v erse reco v ery c u rrent body diode for w ard c u rrent v gs = 10 v * v dd i sd dri v er gate dri v e d.u.t. i sd w a v eform d.u.t. v ds w a v eform ind u ctor c u rrent d = p. w . period + - + + + - - - * v gs = 5 v for logic le v el de v ices peak diode recovery dv/dt test circuit r g v dd ? d v /dt controlled b y r g ? dri v er same type as d.u.t. ? i sd controlled b y d u ty factor "d" ? d.u.t. - de v ice u nder test d.u.t. circ u it layo u t considerations ? lo w stray ind u ctance ? gro u nd plane ? lo w leakage ind u ctance c u rrent transformer
document number: 91000 www.vishay.com revision: 18-jul-08 1 disclaimer legal disclaimer notice vishay all product specifications and data are subject to change without notice. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, ?vishay?), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. vishay disclaims any and all li ability arising out of the use or application of any product describ ed herein or of any information provided herein to the maximum extent permit ted by law. the product specifications do not expand or otherwise modify vishay?s terms and conditions of purcha se, including but not limited to the warranty expressed therein, which apply to these products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of vishay. the products shown herein are not designed for use in medi cal, life-saving, or life-sustaining applications unless otherwise expressly indicated. customers using or selling vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify vishay for any damages arising or resulting from such use or sale. please contact authorized vishay personnel to obtain written terms and conditions regarding products designed for such applications. product names and markings noted herein may be trademarks of their respective owners.
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